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> (2010) Variability in Nanoscale Fabrics: Bottom-up, Integrated Analysis and Mitigation
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(2010) Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation
Источники:
- https://www.umass.edu/nanofabrics/sites/def...ritish_2013.pdf
- ACM Transactions on Computational Logic, Vol. V, No. N, Month 20YY, Pages 1–0??.

Авторы: Pritish Narayanan1, Michael Leuchtenburg1, Jorge Kina2, Prachi Joshi1,Pavan Panchapakeshan1, Chi On Chui2and C. Andras Moritz1
(1 - University of Massachusetts, 2- University of California, Los Angeles)

QUOTE
Emerging nano-device based architectures will be impacted by parameter variation in conjunc-tion with high defect rates.  Variations in key physical parameters are caused by manufacturingimprecision as well as fundamental atomic scale randomness.  In this paper, the impact of param-eter variation on nanoscale computing fabrics is extensively studied through a novel integratedmethodology across device, circuit and architectural levels.  This integrated approach enables tostudy in detail the impact of physical parameter variation across all fabric layers.  A final contri-bution of the paper includes novel techniques to address this impact.  The variability framework,while generic,  is explored extensively on the Nanoscale Application Specific Integrated Circuits(NASICs) nanowire fabric.  For variation ofσ=10% in key physical parameters, the on current isfound to vary by up to 3.5X. Circuit-level delay shows up to 118% deviation from nominal.  MonteCarlo simulations using an architectural simulator found 67% nanoprocessor chips to operate be-low nominal frequencies due to variation.  New built-in variation mitigation and fault-toleranceschemes, leveraging redundancy, asymmetric delay paths and biased voting schemes, were devel-oped and evaluated to mitigate these effects.  They are shown to improve performance by up to7.5X on a nanoscale processor design with variation, and improve performance in designs relyingon  redundancy  for  defect  tolerance  -  without  variation  assumed.  Techniques  show  up  to  3.8Ximprovement in effective-yield performance products even at a high 12% defect rate.  The suite oftechniques provides a design space across key system-level metrics such as performance, yield andarea.


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