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> (2015) Three Scenarios for Evolution of Exascale, Computing/ Erik DeBenedictis
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Three Scenarios for the Evolution of Exascale Computing (2015)
Источники:
- https://www.rdworldonline.com/three-scenari...cale-computing/
- http://www.scientificcomputing.com/blogs/2...scale-computing
Автор: Erik DeBenedictis

QUOTE
Let’s consider three scenarios for the evolution of supercomputers in the range of 1-50 exaflops.

A. Devices and scaling: Efforts continue to extend Moore’s Law in the most seamless way. This scenario assumes continuation of the original Moore’s Law, which predicted a rising number of devices per chip at constant power per unit area (or chip, since chip area has remained fairly constant) and rising speed. The design scaling rule, called Dennard scaling, relies on the operating voltages for silicon circuits to decrease at a rate commensurate with the shrinking of transistors in order to keep power in bounds (power consumption being proportional to the square of the operating voltage). 


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B. 3D: Greater use of 3-D integration as illustrated in diagram B offers tremendous benefit, yet poses technology development challenges and will alter architecture enough to necessitate some reprogramming. Flash memory chips with 32 devices in the third dimension are in production — with the manufacturers boasting that the next generation will be 50+ layers. On the surface, one might think Moore’s Law could be extended into the third dimension using this approach, except that computers cannot be built entirely of memory and the obvious solution of manufacturing computer logic in the third dimension has an insurmountable heat removal problem. Basically, heat can be produced throughout a 3-D solid, but can only be dissipated along a 2-D surface or face.


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С.: Architectural specialization. Progress can continue through architectural changes alone as illustrated in diagram C, yet this could be problematic for software and algorithms. Traditional microprocessor architectures use only a few percent of their energy budget for the actual arithmetic, with the rest attributed to memory access and the interpretation of the processor’s instruction set. Just as a graphics processing unit (GPU) achieves high energy efficiency by using constrained data paths and applying one instruction stream to many ALUs in parallel, other GPU-like specialized devices could be made for other purposes.


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