Студенческий форум -> (2014) Moore’s Law at 10 nm and Beyond

Помощь

Поиск

Участники

Календарь

Новости

Учебные Материалы

ВАЛтест

Фотогалерея

Правила форума

Виртуальные тренажеры

Мемуары

Здравствуйте Гость ( Вход | Регистрация )

Выслать повторно письмо для активации

Студенческий форум -> Студенческие форумы НИЯУ МИФИ -> Азбука наноэлектроники -> Эра "нано": настоящее и будущее. Прогнозы и планы. Масштабирование, разброс характеристик, снижение Еп

(2014) Moore’s Law at 10 nm and Beyond, What Goes Around Comes Around

Подписка на тему | Сообщить другу | Версия для печати

VAL

Дата 22.07.2014 18:04

Offline

Мэтр, проФАН любви... proFAN of love

Профиль
Группа: Администраторы
Сообщений: 37809
Пользователь №: 1
Регистрация: 6.03.2004

What Goes Around Comes Around: Moore’s Law At 10nm And Beyond
Источник: http://semiengineering.com/what-goes-aroun...0nm-and-beyond/
Автор: Greg Yeric

QUOTE

Time to do some stairs
While area scaling from 16nm to 10nm is advertised at 1.9x, the devil’s in the details once you hop off the lithography-enabled scaling ride. And no matter what area scaling you arrive at, it’s going to be offset by a hefty increase in process cost, not to mention an increasingly ornery set of second-order effects such as variation, interconnect parasitics, and reliability. For instance, to surmount the lack of direct scaling in contacted transistors, the industry has already absorbed the costs of 5 new middle-of-line masks, and in 10nm these will need more multiple patterning steps in order to keep shrinking, plus the multiple patterning will now have to extend into the routing layers. Any time you add a multiple patterning mask, you can rest assured that you will back off from the pitch-enabled scaling entitlement (and of course pay more). What’s worse, some of the critical layers may very well need to extend beyond double patterning into triple for 10 and likely quadruple for 7.

And if double patterning can make a designer cry in his beer, then quadruple patterning will make him switch to scotch.

QUOTE

In summary, there are many options that can help in their small way toward further Moore’s Law scaling, but there’s no way around it, the escalator is broken and we are going to climb the stairs. We are going to need to extend our margining focus and we are going to have to deal with an increasingly heterogeneous and complicated system “on chip”. Maybe that will be good for us. The incredible, decades-long, exponential progress of traditional process scaling has perhaps made the rest of the ecosystem a bit soft in the middle (not you, you look great. We both know I’m talking about software engineers). And, while 2014 marks the 49th anniversary of Moore’s original paper, this February marks the 50th anniversary of American Heart Month.

QUOTE

Epilogue
That crying designer (is that redundant?) finally passed out with all the scotch, by the way. Then he had a dream. Directed Self-Assembly had been harnessed to seed uniform semiconducting carbon nanotubes and place them in dense, exact alignment. And then that was repeated in monolithic layers of logic devices. Then even more CNTs were crammed into low-resistance vias and were married to multi-layer graphene wires with dramatically reduced interconnect RC, improved thermal conductivity, and no significant EM constraints. And someone had finally figured out how to place gate contacts over the active area of a device, allowing for a dramatic simplification in physical design. Above that sat a 4F2 crossbar universal memory. All on 450mm wafers with 120 WPH EUV.

--------------------

www.valinfo.ru
Всегда... Always....
Quod licet jovi, non licet bovi!

VAL

Дата 19.02.2019 19:42

Offline

Мэтр, проФАН любви... proFAN of love

Профиль
Группа: Администраторы
Сообщений: 37809
Пользователь №: 1
Регистрация: 6.03.2004

QUOTE

Epilogue

That crying designer (is that redundant?) finally passed out with all the scotch, by the way. Then he had a dream. Directed Self-Assembly had been harnessed to seed uniform semiconducting carbon nanotubes and place them in dense, exact alignment. And then that was repeated in monolithic layers of logic devices. Then even more CNTs were crammed into low-resistance vias and were married to multi-layer graphene wires with dramatically reduced interconnect RC, improved thermal conductivity, and no significant EM constraints. And someone had finally figured out how to place gate contacts over the active area of a device, allowing for a dramatic simplification in physical design. Above that sat a 4F2 crossbar universal memory. All on 450mm wafers with 120 WPH EUV.

Then he woke up.

With a hangover.

At the bottom of the stairs.

And lots of baggage to carry, full of customers’ expectations.

:doh:

--------------------

www.valinfo.ru
Всегда... Always....
Quod licet jovi, non licet bovi!

VAL	Дата 12.10.2022 10:38
Offline Мэтр, проФАН любви... proFAN of love Профиль Группа: Администраторы Сообщений: 37809 Пользователь №: 1 Регистрация: 6.03.2004	:doh: -------------------- www.valinfo.ru Всегда... Always.... Quod licet jovi, non licet bovi!

0 Пользователей читают эту тему (0 Гостей и 0 Скрытых Пользователей)

0 Пользователей:

« Предыдущая тема | Эра "нано": настоящее и будущее. Прогнозы и планы. Масштабирование, разброс характеристик, снижение Еп | Следующая тема »

Powered by Invision Power Board(U) v1.3 Final © 2003 IPS, Inc.
Установка, модификация и поддержка:
Barsum | 1px Design Group & Xac | OппаRU форум