Студенческий форум [Powered by Invision Power Board]

Версия для печати темы
Нажмите сюда для просмотра этой темы в оригинальном формате

Студенческий форум > Базовые кристаллы памяти (перестраиваемая архитектура СБИС ЗУ) > (2016) Lapshinsky V. Emerging achitectures for PIM

Автор: VAL 28.02.2017 10:29

(2016) Lapshinsky V.A. EMERGING ARCHITECTURES FOR PROCESSOR-IN-MEMORY CHIPS: TAXONOMY AND IMPLEMENTATION
Источники:
- http://journals.rudn.ru/engineering-researches/article/view/15320/14084
- Вестник РУДН, серия Инженерные исследования, 2016, No 4, с. 35-40
- https://cyberleninka.ru/article/n/emerging-architectures-for-processor-in-memory-chips-taxonomy-and-implementation
- https://www.researchgate.net/publication/330161511_KIBERNETIKA_I_MEHATRONIKA_EMERGING_ARCHITECTURES_FOR_PROCESSOR-IN-MEMORY_CHIPS_TAXONOMY_AND_IMPLEMENTATION

QUOTE

The emergence of PIM (processing-in-memory) die and Date-Centric systems (DCS) and near-data processing approach (NDP) has given rise to the need of developing architectural taxonomy for multi-core PNM (processing near memory) hardware with multi-level memory structure. PIM die (in Russian technical literature usually used terms chips or crystals) considered as an effective alternative to conventional SRAM/DRAM/Flash-memory on Cache-CPU/Main Memory/Storage Class Memory and Storage levels. In the past decade, a few different methods to classify and to implement PIM die and DCS/NDP systems proposed. These approaches are either software interfacing with computing, hierarchical and massively parallel SIMD processing approaches etc. In this paper, presented summarized prolegomena for PIM die architecture and implementation. In particular, in form of basic PIM chips and nanostores.

Key words:
processing-in-memory; processing near memory; near-data processing; Date-Centric systems; PIM memory taxonomy; basic PIM chips implementation; emerging memories chips and
nanostores

Автор: VAL 22.01.2022 16:12